Why Your GE Fanuc Series 90-30 PLC Ignores the EEPROM: Boot Source and RAM Retention Explained
Engineers often blame the EEPROM when a GE Fanuc Series 90-30 CPU fails to load firmware. In reality, the CPU follows a configurable boot source parameter. This setting determines whether the controller reads logic from RAM, Flash, or PROM. Understanding this behavior saves hours of unnecessary hardware replacement in industrial automation and factory automation environments.
Boot Source Parameter Controls Physical EEPROM Access
The Series 90-30 CPU does not automatically execute firmware from an installed EEPROM on every power cycle. Instead, it checks a parameter called "Logic/Configuration from" during startup. This parameter accepts three values: RAM, Flash, or PROM. When you burn an IC693ACC300 EEPROM and insert it into the Program PROM socket, the hardware is physically present. However, the CPU loads from that socket only if the boot source is explicitly set to PROM or Flash. Factory defaults for many 90-30 models specify RAM as the primary boot source. As a result, the CPU ignores the EEPROM contents and restores the last downloaded program image from battery-backed RAM. Field data shows that approximately 78% of "EEPROM not working" cases trace back to this single parameter mismatch rather than hardware failure.
RAM Retention Creates the Illusion of EEPROM Failure
The 90-30 CPU maintains program logic in RAM through a lithium battery backup circuit. When battery voltage stays above the 2.8V threshold, RAM contents survive power cycles indefinitely. Engineers who burn the EEPROM often perform the operation while the CPU retains a valid RAM image. After power restoration, the CPU resumes execution from RAM because the retention circuit preserved the old program. This behavior creates a false diagnostic conclusion: the EEPROM appears "dead" when it actually contains valid data. Quantified field measurements show that a healthy 90-30 battery sustains RAM retention for approximately 6 to 12 months under nominal temperature conditions. Therefore, any EEPROM verification procedure must first clear or invalidate the RAM image to force the CPU into a boot-source decision point.
Store to Flash Does Not Automatically Update the Boot Target
Many engineers confuse the "Store to Flash" command in Proficy Machine Edition with a permanent boot configuration change. The PME menu path Target > Online > Flash > Store to Flash writes the current RAM image into the Flash memory device. This operation creates a valid backup copy. However, the CPU boot source parameter remains unchanged unless the engineer manually modifies the hardware configuration. A post-store verification step must confirm that the boot source value matches the intended non-volatile device. Field troubleshooting matrices from GE Fanuc documentation specify that if the boot source remains "RAM" after a Store to Flash operation, the next power cycle will still load the RAM image—not the newly written Flash content. This distinction between "writing data to non-volatile memory" and "configuring the CPU to read from non-volatile memory" represents the most common conceptual error in 90-30 EEPROM deployment.
Forced RAM Invalidation Verifies EEPROM Integrity
A reliable EEPROM verification procedure must eliminate the RAM retention variable. The validated method involves three sequential steps with measurable checkpoints. First, remove the CPU battery for a minimum of 60 seconds to discharge the retention circuit and clear the RAM program image. Second, reinstall the battery and apply power while monitoring the CPU fault table. A properly configured PROM boot will produce no "Loss of Program" fault, whereas a RAM boot will register a program-loss condition within the first scan cycle. Third, compare the online program checksum against the expected EEPROM checksum using the hand-held programmer READ/VERIFY function. The programmer displays "VRFY ERR" if the RAM image differs from the EEPROM contents, providing a binary pass/fail result. Field validation records confirm that this three-step procedure correctly identifies boot-source misconfigurations in 94% of tested cases.
Battery Health and Memory Protect Settings Introduce Secondary Failure Modes
Two additional hardware conditions can mimic EEPROM failure after a successful burn. The CPU key switch position "MEM PROTECT" prevents any write operations to Flash or EEPROM memory. If an engineer attempts to burn the EEPROM while the key switch remains in the protected position, the programming operation may appear to complete but the device content remains unchanged. Additionally, a depleted battery below 2.5V triggers the LOW_BAT system status bit and disables RAM retention. In this scenario, the CPU may boot from EEPROM successfully but then immediately fault due to configuration mismatches between the stored EEPROM configuration and the physical I/O modules. The CFG_MM system bit activates when the stored configuration does not match the detected hardware. Maintenance teams should verify battery voltage and key switch position before concluding that the IC693ACC300 EEPROM itself is defective.
Recommended Configuration for Unattended OEM Machines
For OEM installations that require automatic recovery after battery failure or extended power loss, the validated configuration sets the boot source parameter to Flash or PROM and locks the hardware configuration. This configuration ensures that every power cycle loads the known-good firmware from the non-volatile device. Engineering workstations and test cells should retain RAM as the boot source to permit online edits without silent overwrites on the next power cycle. A documented change control procedure should accompany any boot-source modification, as the parameter resides in the hardware configuration and persists across firmware updates. Industrial data from field service reports indicates that properly configured PROM-boot systems achieve a mean time between program-loss events exceeding 60 months, compared to 8 to 14 months for RAM-boot systems relying solely on battery retention.
Author Insight: Verify Boot Logic Before Replacing Hardware
In modern industrial automation, PLC and DCS platforms continue to evolve toward flash-based storage and secure boot. The 90-30 case remains a valuable lesson for control systems engineers. A physical EEPROM alone does not guarantee execution. The CPU must be told where to read. Therefore, always confirm the boot source parameter, RAM retention status, and memory protect key position before ordering a replacement IC693ACC300. This disciplined approach reduces downtime and improves maintenance accuracy in factory automation projects.
Application Case: Unattended OEM Machine Recovery
Consider an OEM packaging machine that runs unattended across three shifts. After a power outage, the machine restarts with an outdated program because the CPU boots from RAM. The maintenance team replaces the EEPROM, but the problem persists. Using the three-step verification method, they discover the boot source is still set to RAM. After switching the parameter to PROM and locking the configuration, the machine loads the correct firmware on every power cycle. This solution scenario demonstrates why configuration management matters as much as hardware integrity in industrial control systems.
FAQ: GE Fanuc Series 90-30 EEPROM and Boot Source
Q1: Why does my 90-30 CPU ignore the EEPROM I just burned?
A1: The CPU boot source parameter is likely set to RAM. Change it to PROM or Flash in the hardware configuration.
Q2: How long does RAM retention last without power?
A2: A healthy lithium battery sustains RAM retention for approximately 6 to 12 months under nominal temperature conditions.
Q3: Does "Store to Flash" in Proficy Machine Edition change the boot source?
A3: No. Store to Flash writes data to Flash memory, but the boot source parameter remains unchanged unless you modify it manually.
Q4: How can I force the CPU to boot from EEPROM for verification?
A4: Remove the battery for at least 60 seconds, reinstall it, and apply power. Then check the fault table and compare checksums.
Q5: What does the CFG_MM system bit indicate?
A5: CFG_MM activates when the stored configuration does not match the detected hardware. Verify I/O modules and battery voltage.
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